semiconductor 1 features ? multifunction capability - binary to 1 of 4 decoders or 1 to 4 line demultiplexer ? active low mutually exclusive outputs ? fanout (over temperature range) - standard outputs . . . . . . . . . . . . . . . 10 lsttl loads - bus driver outputs . . . . . . . . . . . . . 15 lsttl loads ? wide operating temperature range . . . -55 o c to 125 o c ? balanced propagation delay and transition times ? signi?cant power reduction compared to lsttl logic ics ? hc types - 2v to 6v operation - high noise immunity: n il = 30%, n ih = 30%of v cc at v cc = 5v ? hct types - 4.5v to 5.5v operation - direct lsttl input logic compatibility, v il = 0.8v (max), v ih = 2v (min) - cmos input compatibility, i l 1 m a at v ol , v oh ? memory decoding, data routing, code conversion description the harris cd74hc139, cd74hct139 contain two independent binary to one of four decoders each with a single active low enable input ( 1e or 2e). data on the select inputs (1a0 and 1a1 or 2a0 and 2a1) cause one of the four normally high outputs to go low. if the enable input is high all four outputs remain high. for demultiplexer operation the enable input is the data input. the enable input also functions as a chip select when these devices are cascaded. this device is functionally the same as the cd4556b and is pin compatible with it. the outputs of these devices can drive 10 low power schottky ttl equivalent loads. the 74hct logic family is functionally as well as pin equivalent to the 74ls logic family. pinout cd74hc139, cd74hct139 (pdip, soic) top view ordering information part number temp. range ( o c) package pkg. no. cd74hc139e -55 to 125 16 ld pdip e16.3 CD74HCT139E -55 to 125 16 ld pdip e16.3 cd74hc139m -55 to 125 16 ld soic m16.15 notes: 1. when ordering, use the entire part number. add the suf?x 96 to obtain the variant in the tape and reel. 2. die is available which meets all electrical specifications. please contact your local sales office or harris customer service for ordering information. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 1e 1a0 1a1 1y0 1y1 1y2 gnd 1y3 v cc 2a0 2a1 2y0 2y1 2y2 2y3 2e september 1997 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright ? harris corporation 1997 cd74hc139, cd74hct139 high speed cmos logic dual 2-to-4 line decoder/demultiplexer file number 1545.1
2 functional diagram logic diagram truth table inputs enable select outputs ea1a0 y3 y2 y1 y0 0001110 0011101 0101011 0110111 1xx1111 note: x = dont care, logic 1 = high, logic 0 = low a0 2 (14) 3 (13) 4 (12) y3 y0 a1 1 (15) e 5 (11) 6 (10) 7 (9) y1 y2 4 (12) 5 (11) y0 y1 6 (10) y2 7 (9) y3 2 (14) a0 3 (13) a1 1 (15) e cd74hc139, cd74hct139
3 absolute maximum ratings thermal information dc supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 7v dc input diode current, i ik for v i < -0.5v or v i > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . 20ma dc output diode current, i ok for v o < -0.5v or v o > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 20ma dc output source or sink current per output pin, i o for v o > -0.5v or v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 25ma dc v cc or ground current, i cc or i gnd . . . . . . . . . . . . . . . . . . 50ma operating conditions temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c supply voltage range, v cc hc types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2v to 6v hct types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5v to 5.5v dc input or output voltage, v i , v o . . . . . . . . . . . . . . . . . 0v to v cc input rise and fall time 2v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (max) 4.5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (max) 6v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (max) thermal resistance (typical, note 3) q ja ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. note: 3. q ja is measured with the component mounted on an evaluation pc board in free air. dc electrical speci?cations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hc types high level input voltage v ih - - 2 1.5 - - 1.5 - 1.5 - v 4.5 3.15 - - 3.15 - 3.15 - v 6 4.2 - - 4.2 - 4.2 - v low level input voltage v il - - 2 - - 0.5 - 0.5 - 0.5 v 4.5 - - 1.35 - 1.35 - 1.35 v 6 - - 1.8 - 1.8 - 1.8 v high level output voltage cmos loads v oh v ih or v il -0.02 2 1.9 - - 1.9 - 1.9 - v -0.02 4.5 4.4 - - 4.4 - 4.4 - v -0.02 6 5.9 - - 5.9 - 5.9 - v high level output voltage ttl loads - - --- - - - - v -4 4.5 3.98 - - 3.84 - 3.7 - v -5.2 6 5.48 - - 5.34 - 5.2 - v low level output voltage cmos loads v ol v ih or v il 0.02 2 - - 0.1 - 0.1 - 0.1 v 0.02 4.5 - - 0.1 - 0.1 - 0.1 v 0.02 6 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads - - --- - - - - v 4 4.5 - - 0.26 - 0.33 - 0.4 v 5.2 6 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc or gnd -6-- 0.1 - 1- 1 m a quiescent device current i cc v cc or gnd 0 6 - - 8 - 80 - 160 m a cd74hc139, cd74hct139
4 hct types high level input voltage v ih - - 4.5 to 5.5 2- - 2 - 2 - v low level input voltage v il - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 v high level output voltage cmos loads v oh v ih or v il -0.02 4.5 4.4 - - 4.4 - 4.4 - v high level output voltage ttl loads -4 4.5 3.98 - - 3.84 - 3.7 - v low level output voltage cmos loads v ol v ih or v il 0.02 4.5 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads 4 4.5 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc and gnd 0 5.5 - 0.1 - 1- 1 m a quiescent device current i cc v cc or gnd 0 5.5 - - 8 - 80 - 160 m a additional quiescent device current per input pin: 1 unit load (note 4) d i cc v cc -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 m a note: 4. for dual-supply systems theoretical worst case (v i = 2.4v, v cc = 5.5v) specification is 1.8ma. dc electrical speci?cations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hct input loading table input unit loads all 0.7 note: unit load is d i cc limit speci?ed in dc electrical table, e.g., 360 m a max at 25 o c. switching speci?cations input t r , t f = 6ns parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max hc types propagation delay t plh, t phl c l = 50pf 2 - - 145 - 180 - 220 ns a0, a1 to outputs 4.5 - - 29 - 36 - 44 ns 6 - - 25 - 31 - 38 ns e to outputs t plh, t phl c l = 50pf 2 - - 135 - 170 - 205 ns 4.5 - - 27 - 34 - 41 ns 6 - - 23 - 29 - 35 ns select to output t plh, t phl c l = 15pf 5 - 12 - - - - - ns enable to output t plh, t phl c l = 15pf 5 - 11 - - - - - ns cd74hc139, cd74hct139
5 output transition time (figure 1) t tlh , t thl c l = 50pf 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns power dissipation capacitance, (notes 5, 6) c pd - 5 -55- - - - - pf input capacitance c in - - - - 10 - 10 - 10 pf hct types propagation delay a0, a1 to outputs t plh , t phl c l = 50pf 4.5 - - 34 - 43 - 51 ns e to outputs t plh , t phl c l = 50pf 4.5 - - 34 - 43 - 51 ns select to output t plh, t phl c l = 15pf 5 - 14 - - - - - ns enable to output t plh, t phl c l = 15pf 5 - 14 - - - - - ns output transition time (figure 2) t tlh , t thl c l = 50pf 4.5 - - 15 - 19 - 22 ns power dissipation capacitance, (notes 5, 6) c pd - 5 -59- - - - - pf input capacitance c in - - - - 10 - 10 - 10 pf notes: 5. c pd is used to determine the dynamic power consumption, per decoder/demux. 6. p d = v cc 2 f i (c pd + c l ) where: f i = input frequency, c l = output load capacitance, v cc = supply voltage. switching speci?cations input t r , t f = 6ns (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max test circuits and waveforms figure 1. hc and hcu transition times and propaga- tion delay times, combination logic figure 2. hct transition times and propagation delay times, combination logic t phl t plh t thl t tlh 90% 50% 10% 50% 10% inverting output input gnd v cc t r = 6ns t f = 6ns 90% t phl t plh t thl t tlh 2.7v 1.3v 0.3v 1.3v 10% inverting output input gnd 3v t r = 6ns t f = 6ns 90% cd74hc139, cd74hct139
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